1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems that are implemented using pipeline techniques and a store through (write through) cache strategy Apparatus and method for processing instructions in a period between the time of completion of a write instruction operand address and the time of completion of the write instruction operand are described.
2. Description of the Related Art
The pipeline technique is widely used to increase the performance of data processing units. In this technique the data processing unit is partitioned into various segments, each segment processing a portion of an instruction for a selected period of time. Using this technique, the execution of an individual instruction will typically require a longer time in a pipelined system than execution of an instruction in a non-pipelined data processing unit. However, an instruction can be completed during each selected period of time in the pipelined data processing system, thereby increasing the rate of instruction execution in a pipelined data processing unit.
The increased instruction execution rate is achieved by maintaining an orderly sequence of instruction execution. However, operand processing operations, typically performed in an execution unit of a data processing unit, can take varying amounts of time. The pipelining technique can accommodate this processing time variability by providing a sufficiently long selected period of time to permit any possible operation by the execution to be completed in the selected period of time. This solution adversely impacts the performance of the data processing system. A second solution to execution unit processing time variability is to provide a relatively short execution unit selected period of time and suspend processing of other instruction segments for operations in the execution unit requiring longer periods of time. This approach, relatively easy to implement in a pipelined data processing unit, results in portions of the data processing unit being idle for substantial periods of time. Finally, the problem of processing time variability by the execution unit can be addressed by parallel (execution) processing units along with control apparatus to reassemble the resulting operands in correct sequence This approach requires substantial additional apparatus in the data processing unit and a substantial increase in control functionality to prevent compromise of the processing operations.
The operations involving increased execution time by the execution unit can impact the performance of the data processing unit in the following manner. The processing of a write instruction can result in the associated operand address, even when processed in a virtual memory environment (i.e., the data processing unit associates a virtual address with an operand while the execution cache unit and the main memory unit typically associates a real address with an operand, the translation of addresses taking place in a virtual memory management unit) that is completed at an earlier time than the completion of the associated operand itself In the store through (write through) cache strategy of the preferred environment of the present invention, the real address is required for storage in the main memory unit. During the associated delay, processing of instructions involving the execution unit is suspended pending completion of the operand.
A need has therefore been felt for apparatus and a related technique to permit a cache unit associated with an execution unit of a pipelined data processing unit to continue processing operations in the interval between the availability of an operand address associated with a write instruction and the availability of the operand associated with the write instruction.